Is it a strong business proposition? 

Absolutely, yes! Collaboration never fails!

Here is what McKinsey & Company said recently on this line:

//A focus on leading-edge chips and the machinery required to create them/

For semiconductor manufacturers, creating smaller node sizes has traditionally been the path to success. For decades, the number of transistors on a chip doubled every two years—the rate predicted by Moore’s law—as semiconductor companies constantly decreased the size of technology nodes. In recent years, however, the rate of doubling has slowed because technological challenges increase as the industry approaches the physical limits for the number of transistors that can be included on a single chip. Nevertheless, companies will still attempt to push the technology, because average demand growth for chips with the smallest nodes—seven nanometers (nm) and below—will be four percentage points higher than supply growth through 2025.

The importance of node size varies by device segment, and the demand for leading-edge chips will grow much more in some categories than in others. Since customers expect high performance for compute-intensive applications, semiconductor companies that design chips in the smallest available technology node may have a distinct advantage in these areas. In other segments, larger nodes are often suitable because customers are satisfied with current chip performance or require specific features, such as fast switching, and see little advantage in moving to smaller node sizes.

//Differentiation through ‘more than Moore’/

Beyond reducing structure size, some semiconductor companies are pursuing “more than Moore” innovations to make their products distinctive. Some, for instance, are developing semiconductors based on materials other than silicon. Compound semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN), are particularly well suited for applications requiring both high power and frequency, since they limit energy loss and allow for the creation of smaller form factors. The push for increased sustainability and electrification is spurring the adoption of SiC and GaN power devices, and the compound annual growth rate (CAGR) for both categories is expected to far exceed the 5 percent growth forecasted for the power semiconductor market as a whole. In the base-case scenario, annual market growth is expected to be 23 percent for SiC devices and 40 percent for GaN power devices.

A focus on innovative features may be particularly valuable in high-growth segments, such as the Internet of Things, because it helps differentiate products from competitors (for instance, by optimizing the fast switching required in several radio frequency applications). Several IDMs and foundries are already developing such products in mature nodes.

//Advanced packaging of semiconductor components/

These techniques provide better heat management during operations, allowing companies to place semiconductor components closer together. With a greater number of connection points, these chips provide higher data-transfer rates and better performance. In addition, advanced packaging allows semiconductor companies to combine mature and leading-edge chips in an integrated system for applications that need both types, which lowers costs. This trend, called heterogeneous integration, enables companies to combine multiple smaller chips instead of making one large chip. Larger chips often have lower yield, with the drop typically scaling with chip size, so heterogeneous integration may deliver profound cost benefits.

The advanced-packaging market was valued at $20 billion in 2020, and this figure is expected to rise to $45 billion by 2026, when it will represent about 50 percent of packaging revenues. Although leading-edge IDMs and foundries are driving packaging innovations, advanced techniques also create opportunities for other players across the value chain because they boost demand for new materials and new equipment. 

//Specialized applications/

Application-specific integrated chips (ASIC) integrate well-defined algorithms and functions into their chip design and are customized for specific purposes, such as for use in artificial intelligence and cloud computing. The segment has recently grown significantly and could offer a good opportunity for additional players. Small companies that want to focus on developing specialized semiconductors could still find their products in high demand, even if their customer base is relatively small. The customer base for ASICs includes many different companies, such as automotive OEMs and hyperscalers, and their needs will vary. Some customers may decide to design their own ASICs in-house to improve customization, differentiate their products, and reduce lead times. They would then work directly with foundries for their manufacturing needs. Other players, typically smaller ones, prefer to have an ASIC partner that is responsible for all steps needed to move from design to end product because this requires many specialized competencies.

//A strong talent pipeline/

As semiconductors become more critical to product differentiation, some electronics companies, automotive OEMs, and hyperscalers are moving chip design in-house to increase customization and eliminate bottlenecks. These moves are making competition for already-scarce semiconductor talent even tougher than usual. Simultaneously, chip design is becoming more and more complex as the functions of semiconductors expand, which requires more labor. The increase in labor is especially high with five-nm nodes, which are the most difficult to design and require the most days of labor.

With greater competition, semiconductor companies would be wise to increase their efforts to recruit talent, including staff with expertise in process technology and operations management. As semiconductor companies step up recruitment, they may need to build their brand. Typically, semiconductor products receive less attention than end products, and prospective employees may have little knowledge of the many strong and innovative companies within the sector. Companies might also need to review compensation and learning and development opportunities to ensure that they are on par with businesses in other industries. One possible solution to the labor shortage might involve forming partnerships with academic institutions, especially in markets where talent is in very short supply. If semiconductor companies consider supporting learning programs, and perhaps provide guidance on classes offered, graduates are more likely to have the skills required to work in the industry.

/Improved collaboration within the semiconductor ecosystem/

The increased complexity of chip design, combined with shifts in the value chain and greater competition for talent, have increased the importance of ecosystem building within the semiconductor industry. Partnerships with customers are already becoming more common. For instance, many automotive OEMs that want to improve their design capabilities are now collaborating with semiconductor companies, especially on the development of application-specific solutions, such as those for autonomous vehicles.

In another type of collaboration, companies may create ecosystems in which one player develops intellectual-property (IP) blocks that many customers can leverage. Arm, for instance, has developed an architecture for a processor that others may license. This strategy decreases costs for all involved. Some companies have also formed strong IP partnerships with academic institutions.

Major semiconductor players also have a long history of joining forces to develop and align their technology blocks, thereby reducing the chance that one organization will create a technology that does not fit into the value chain. Similarly, industry associations can play an important role in providing guidance on the long-term technology road maps, and dedicated semiconductor research institutes, such as Imec, in Belgium, may convene players to collaborate during precompetitive research.

Beyond partnerships, semiconductor companies might want to undertake a programmatic M&A strategy—a serial approach to smaller acquisitions, along a specific theme—as the industry consolidates. If they do so, they might benefit by focusing on acquisitions that would allow them to branch into adjacent areas, open important markets, or add capabilities essential for future growth and for extending their technology leadership. The current scarcity of targets, however, requires potential acquirers to investigate and execute mergers quickly.

Collaboration with other ecosystem members could also take more informal shapes. If multiple semiconductor companies agree to build or expand hubs for design and manufacture, they could have an easier time attracting talent and might obtain other benefits, such as the ability to collaborate on IP development.

For some semiconductor companies, capacity expansion could deliver benefits. But given the enormous sums required for construction and equipment, company leaders must carefully consider plant capacity before moving ahead. Operating and construction costs, when indexed per 12-inch mask layer, fall as capacity increases. For instance, indexed construction and operating costs are both around $3 billion for fabs with a capacity of 250,000 layer starts per week (LSPW). Indexed construction costs drop to between $2 billion and $3 billion for fabs with a capacity of 400,000 LSPW, after which they plateau. Operating costs reach a plateau for fabs with a capacity of around 575,000 LSPW.

Our analysis suggests that fabs with a capacity of at least 600,000 LSPW generate the best cost position. This would correspond to 12,000 to 20,000 wafer starts per week, depending on the product. The type of chip being produced will significantly affect costs, which increase exponentially as node size shrinks. Building a 40-nm fabrication plant with a capacity of at least 600,000 LSPW would likely require around $5 billion, with about 80 percent of the investment going to equipment expenses. But leading-edge fabs producing the smallest node sizes might cost $10 billion or more.

//Fab scaling/

Today, semiconductor manufacturers will often build large fabs with extensive production lines. Only a few years ago, a fab with 20,000 wafer starts per week (wspw) was a big deal. Now leading fabs routinely scale production to deliver 100,000 wspw.

Beyond increasing output, large fabs confer many other advantages. At the building stage, they have lower costs per square meter. A fab’s shell accounts for a relatively small proportion of the total investment; the real cost drivers at new fabs are cleanroom technologies and manufacturing equipment.

After the construction phase, large-scale operations can reduce overhead and increase labor productivity, decreasing the cost per wafer. For instance, companies will be able to centralize some production functions, such as industrial engineering, as well as some support functions, such as human resources and accounting. Companies operating two smaller fabs would have duplicative functions at each site and higher costs. Labor productivity will also increase because direct manufacturing staff, such as members of the maintenance and engineering teams, will have less downtime. If one area or production line is slow, their services will likely be needed elsewhere. These lower overhead costs, combined with greater profits from the larger outputs, will increase a semico’s profits.

//A tough market for all but a few/

The semiconductor industry’s record of steady technological improvement has created a winner-take-all dynamic that makes leading-edge capabilities vital within several segments. If a company’s product or service is even slightly better than a competitor’s, it typically captures an outsize portion—or even the vast majority—of industry revenue. This phenomenon is apparent along the entire value chain, from equipment production to chip manufacture. Companies that want to challenge the winner may find it difficult to catch up, since the leading players are often several years ahead in technology development.

A particular business—or even a group of businesses within a region—may become a hub of expertise (Exhibit 2). Consider a few examples of company- and market-specific strengths:

• Intel dominates the market for desktop and laptop CPUs.

• Qualcomm is the leader in the smartphone system-on-a-chip market.

• TSMC in Taiwan is the top manufacturer for chips at ten nm or below.

• ASML, a Dutch company, produces most lithography equipment, especially leading-edge products.

• Samsung in Korea leads the memory market.

• NVIDIA in the United States dominates the market for graphics cards.

• Almost all specialty chemicals used in semiconductor manufacture come from Japan.

• Japanese and South Korean companies produce the majority of wafers.

While specialization confers competitive advantages, it also means that semiconductor companies and related businesses are highly interdependent. Today, no local market or company has all the capabilities required for end-to-end semiconductor design and manufacturing. If there is a major disruption to the supply chain, similar to what has happened in 2020 because of the COVID-19 crisis, production bottlenecks could occur and certain chips could be in short supply.